This invention generally relates to photoresist methods for forming semiconductor features and more particularly to a bi-layer photoresist dry development method for high resolution features included in a continuous process including reactive ion etching.
In semiconductor fabrication, various layers of insulating material, semiconducting material and conducting material are formed to produce a multilayer semiconductor device. The layers are patterned to create features that taken together, form elements such as transistors, capacitors, and resistors. These elements are then interconnected to achieve a desired electrical function, thereby producing an integrated circuit (IC) device. The formation and patterning of the various device layers are achieved using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth of silicon, lithography, etching, and planarization.
As devices continue to shrink in size, the limits of processing technologies are reached requiring new and cost effective innovations. For example, acceptable photoresist imaging is one limiting technology that has required the adoption of new approaches as finer imaging resolutions are sought to meet the requirements of smaller device sizes. For example, single layer photoresist layers have the problem that they need both effective etching resistance and depth of focus (DOF) requirement. However, the former requirement calls for thicker photoresist layers while the latter requirement calls for thinner photoresist layers. One approach has been to move to bi-layer and tri-layer photoresist layers where the uppermost photoresist layer is used for imaging thereby allowing a thinner image layer and acceptable depth of focus (DOF) with a larger photo-window. Consequently, resolution, and pattern width control are enhanced.
A corresponding requirement to achieve high resolution features and critical dimension control is an effective development process. Wet processing techniques have increasingly become inadequate due to several problems including photoresist poisoning of features by leaving undeveloped photoresist caused by either or both, step height limitations affecting the photo imaging process or by residual nitrogen contaminating species interfering with photoresist exposure and development processes.
As such, dry development processes involving plasma etching have been increasingly adopted leading to improved etching profiles. However, dry etching (plasma etching) has demonstrated problems of its own including, for example, critical dimension bias between isolated and dense line areas where, due to microloading, isolated lines etch faster than dense lines leading to unacceptable differences in critical dimension. For example, in single layer photoresists, dry development of, for example, via holes, leads to roughened hole edges or xe2x80x9cstriationxe2x80x9d. If a hard mask, such as a metal nitride, is used over the inter-layer dielectric (ILD) insulating layer, the via hole edges are tapered to wider dimension referred to as xe2x80x9ctop CD blow outxe2x80x9d. Bi-layer approaches have led to some improvement in dry etching critical dimension control, however, further improvement is need in etching selectivity in dry development as resolution demands are increased, for example with 193 nm and 157 nm photoresists.
For example, more recent shorter wavelength photoresist approaches have used a surface modification technique where the surface of a photoresist film is silylated after the exposure to light. Following exposure, a dry development process is used to form a pattern having good resolution and resistance to dry etching. According to this technique, an initial pattern is formed in a region of about 1000 Angstroms of thickness within of the photoresist film. The silylated surface layer is intended to protect the lower layer from premature etching thus resulting in better selectivity and smoother etching profiles following dry etching of a feature. However, at the dry development stage, the plasma etching procedure according to the prior art has the shortcoming that the sidewalls of the underlying photoresist layer may be over-etched, causing a tapered cross section and loss of critical dimension. Sidewall etching of the underlying photoresist layer in the bi-layer approach with surface layer silylation is believed to occur since the silylation is limited to about the first 200 to 300 Angstroms adjacent the surface of the upper photoresist layer. As a result, the stability of the pattern deteriorates as the dry etching development process proceeds through the photoresist layers.
In the prior art, the dry development etching process has used a sulfur dioxide (SO2) based chemistry including oxygen (O2). Sulfur dioxide (SO2) based chemistry in dry development forms a passivating layer on the sidewalls of the photoresist layers thereby, in theory, increasing the anisotropicity of the etching process to reduce the microloading effects. However, as mentioned, the sulfur dioxide dry development chemistry has limitations, including continued problems with loss of critical dimension during dry development.
For example, one problem associated with the sulfur dioxide (SO2) based chemistry dry development of the prior art include corrosive effects believed to be related to the formation of sulfuric acid, e.g. (H2SO4) leading to corrosion of, for example, copper-filled vias and trenches causing degradation of the copper layers to include peeling of the copper layers. In addition, other features of multi-layer semiconductor devices included in a semiconductor process wafer are generally adversely affected by corrosive action. Yet another adverse effect associated with sulfur dioxide (SO2) based chemistry in dry development processes is the formation of water (H2O) during the dry development process leading to moisture adsorption by low-k (dielectric constant) layers and subsequently to via poisoning.
Another problem with prior art dry development processes is the requirement that photoresist dry development, photoresist layer removal (ashing), and feature etching typically require separate plasma reactors due the large number of residual particles generated during the ashing or feature etching process. Consequently there is a high probability of contamination in the photoresist dry development of the prior art if for example, an ashing process in a separate chamber follows dry development prior to feature etching whereby movement of the semiconductor wafer from one plasma chamber to another increases the likelihood of particle contamination. As a result, the dry development procedure according to the prior art is equipment and time intensive, with residual particle contamination issues, leading to higher manufacturing expense.
There is therefore a need in the semiconductor processing art to develop a more reliable bi-layer photoresist dry development process with high resolution that may be carried out without the corrosion problems and particle contamination problems associated with the prior art dry development methods.
It is therefore an object of the invention to provide to develop a more reliable bi-layer photoresist dry development process with high resolution that may be carried out without the corrosion problems and particle contamination problems associated with the prior art dry development methods while overcoming other shortcomings and deficiencies in the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for semiconductor device feature development using a bi-layer photoresist.
In a first embodiment according to the present invention, a method is provided including the steps of providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least hydrogen and carbon monoxide.
In another embodiment, the plasma reactor includes at least one RF power source for plasma excitation and at least one RF power source for accelerating plasma generated ions towards the substrate surface.
In a related embodiment, the non-silicon containing photoresist layer comprises a non-photoactive polymer.
In another related embodiment, the ambient mixture includes about 1 part hydrogen and about 10 to about 100 parts carbon monoxide, a remaining balance of said ambient mixture further including Argon to total 100 parts. Further yet, the activating light source has a wavelength of one of about 157 nanometers and about 193 nanometers.
In another related embodiment, the non-silicon containing photoresist layer has a thickness greater than the silicon containing photoresist layer. Further, the non-silicon containing photoresist layer has a thickness of about 1000 Angstroms to about 5000 Angstroms and the silicon containing photoresist layer has a thickness of about 500 Angstroms to about 3000 Angstroms.
In another embodiment, the method further includes the step of removing the silicon containing photoresist layer according to a first in-situ ashing process following the step including dry developing. Further, the first in-situ ashing process includes igniting an oxygen containing plasma said oxygen containing plasma further including at least one of nitrogen and fluorine ions said oxygen containing plasma being optimized to simultaneously clean plasma contact surfaces.
In another embodiment, the method further includes the step of etching a semiconductor feature through at least a portion of the substrate according to a reactive ion etch process. Further, the semiconductor feature includes at least one of a via hole, a trench line, a contact hole, a shallow trench isolation feature, and a polysilicon gate feature.
In another embodiment, the method further includes the step of removing the non-silicon containing photoresist layer according to a second in-situ ashing process. Further, the second in-situ ashing process further includes igniting an oxygen containing plasma further including at least one of nitrogen and fluorine, the oxygen containing plasma being optimized to simultaneously clean plasma contact surfaces. Further yet, the second in-situ cleaning process includes maintaining the oxygen containing plasma at an ambient pressure of about 5 to about 20 mTorr, supplying power to the first RF power source at about 200 to about 300 Watts, and supplying power to the second RF power source at about 100 to about 150 Watts.
In another embodiment, the method further includes the step of reactively ion etching through a thickness of a metal nitride layer included in the substrate using a hydrofluorocarbon containing plasma to at least partially form the semiconductor feature.
In another embodiment, the method further includes the step of performing an in-situ cleaning process including igniting an oxygen containing plasma further including at least one of nitrogen and fluorine said oxygen containing plasma being optimized to clean plasma contact surfaces. Further yet, the insitu cleaning process includes operating the oxygen containing plasma at an ambient pressure of about 5 to about 20 mTorr, supplying power to the first RF power source at about 200 to about 300 Watts, and supplying power to the second RF power source at about 100 to about 150 Watts.
In another embodiment, the step including the first in-situ ashing process is combined with the step including the second in-situ ashing process following the step of etching the semiconductor feature to remove the silicon containing photoresist layer and the non-silicon containing photoresist layer.
In another embodiment, the step of the step of etching a semiconductor feature further includes etching through an insulating layer with a dielectric constant of less than about 3 included in the substrate.
In another embodiment, the steps including dry developing, the first in-situ ashing process, the reactive ion etch process, the second in-situ-ashing process, and the in-situ cleaning process are carried out in the plasma reactor according to a continuous process.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.